Soft Error Rate Analysis For Sequential Circuits

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Soft Error Rate Analysis for Sequential Circuits* Natasa Miskov-Zivanov, Diana Marculescu Department of Electrical and Computer Engineering Carnegie Mellon University

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IEEE Spectrum – Engineers at the University of Minnesota are nearing a solution that could help bring down the rate of so-called. be too sensitive to soft errors. There are no tools right now “that combine radiation data with circuit analysis and system.

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H. Asadi and M.B. Tahoori, “Analytical Techniques for Soft Error Rate. “CLASS: Combined Logic and Architectural Soft Error Sensitivity Analysis”, 18th Asia. Approach to Multi-Cycle Soft Error Rate Estimation of Sequential Circuits”, 13th.

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Official Full-Text Paper (PDF): Soft Error Rate Analysis for Sequential Circuits

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365 Modeling the effect of technology trends on the soft error rate of combinatorial logic – Shivakumar, Keckler, et al. – 2002

1.2.1 Analysis and Mitigation of Soft Errors in Logic…. 4. The Soft Error Rate (SER) of a node in a logic circuit is the failure rate of the node due. combinational and sequential logic were discussed in [Buckner et al., 1997]. A study of.

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gates (combinational logic) than flip-flops (sequential logic), the impact attributed to. In Section 3, we introduce the SER analysis engine used in this paper. Section 4. removal the soft error rate of a circuit may vary, we rely on estimating the.

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Feb 3, 2005. soft-error rates for enterprise servers and network- ing hardware. rates of individual elements such as SRAMs, sequential ele-. logic, and factors that depend on the circuit design and the. No systematic analysis. –.

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Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases.

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